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ltc2205-14 1 220514fa 14-bit, 65msps adc the ltc ? 2205-14 is a sampling 14-bit a/d converter de- signed for digitizing high frequency, wide dynamic range signals up to input frequencies of 700mhz. the input range of the adc can be optimized with the pga front end. the ltc2205-14 is perfect for demanding communications applications, with ac performance that includes 78.3db snr and 98db spurious free dynamic range (sfdr). ultralow jitter of 90fs rms allows undersampling of high input frequencies with excellent noise performance. maximum dc specs include 1.5lsb inl, 1lsb dnl (no missing codes). a separate output power supply allows the cmos output swing to range from 0.5v to 3.6v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed with a wide range of clock duty cycles. telecommunications receivers cellular base stations spectrum analysis imaging systems ate sample rate: 65msps 78.3db snr and 98db sfdr (2.25v p-p range) sfdr >90db at 140mhz (1.5v p-p input range) pga front end (2.25v p-p or 1.5v p-p input range) 700mhz full power bandwidth s/h optional internal dither optional data output randomizer single 3.3v supply power dissipation: 600mw optional clock duty cycle stabilizer out-of-range indicator pin compatible family 105msps: ltc2207 (16-bit), ltc2207-14 (14-bit) 80msps: ltc2206 (16-bit), ltc2206-14 (14-bit) 65msps: ltc2205 (16-bit) 40msps: ltc2204 (16-bit) 48-pin (7mm 7mm) qfn package ltc2205-14: 32k point fft, f in = 5.1mhz, C1dbfs, pga = 0, dith = 0 features descriptio u applicatio s u typical applicatio u ? + s/h amp correction logic and shift register output drivers 14-bit pipelined adc core internal adc reference generator 1.25v common mode bias voltage clock/duty cycle control d13 d0 enc pga shdn dith mode oe rand enc v cm analog input 220514 ta01 0.5v to 3.6v 3.3v 3.3v sense ognd ov dd 2.2 f 0.1 f v dd gnd adc control inputs ain + ain ? of clkout 0.1 f 0.1 f 0.1 f , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g04 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30
ltc2205-14 2 220514fa parameter conditions min typ max units resolution (no missing codes) 14 bits integral linearity error differential analog input (note 5) 0.6 1.5 lsb differential linearity error differential analog input 0.2 1 lsb offset error (note 6) 1 8.5 mv offset drift 10 v/ c gain error external reference 0.3 1.9 %fs full-scale drift internal reference 30 ppm/c external reference 10 ppm/c transition noise 0.7 lsb rms package/order information converter characteristics absolute maximum ratings supply voltage (v dd ) ................................... C0.3v to 4v digital output ground voltage (ognd) ........ C0.3v to 1v analog input voltage (note 3) ......C0.3v to (v dd + 0.3v) digital input voltage .....................C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation ............................................ 2000mw operating temperature range ltc2205-14c ........................................... 0c to 70c ltc2205-14i ........................................ C40c to 85c storage temperature range .................. C65c to 150c digital output supply voltage (ov dd ) .......... C0.3v to 4v ov dd = v dd (notes 1 and 2) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) top view uk package 48-lead (7mm 7mm) plastic qfn sense 1 v cm 2 v dd 3 v dd 4 gnd 5 ain + 6 ain ? 7 gnd 8 enc + 9 enc ? 10 gnd 11 v dd 12 36 ov dd 35 d9 34 d8 33 d7 32 d6 31 ognd 30 clkout + 29 clkout ? 28 d5 27 d4 26 d3 25 ov dd 48 gnd 47 pga 46 rand 45 mode 44 oe 43 of 42 d13 41 d12 40 d11 39 d10 38 ognd 37 ov dd v dd 13 v dd 14 gnd 15 shdn 16 dith 17 nc 18 nc 19 d0 20 d1 21 d2 22 ognd 23 ov dd 24 49 t jmax = 125c, ja = 29c/w exposed pad is gnd (pin 49), must be soldered to pcb board order part number uk part marking ltc2205cuk-14 ltc2205iuk-14 ltc2205uk-14 ltc2205uk-14 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges.
ltc2205-14 3 220514fa symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 3.135v v dd 3.465v 1.5 to 2.25 v p-p v in, cm analog input common mode differential input (note 7) 1 1.25 1.5 v i in analog input leakage current 0v a in + , a in C v dd C1 1 a i sense sense input leakage current 0v sense v dd C3 3 a i mode mode pin pull-down current to gnd 10 a c in analog input capacitance sample mode enc + < enc C 6.5 pf hold mode enc + > enc C 1.8 pf t ap sample-and-hold 0.7 ns aperature delay time t jitter sample-and-hold 90 fs rms aperature delay time jitter cmrr analog input 1v < (a in + = a in C ) <1.5v 60 db common mode rejection ratio bw-3db full power bandwidth 700 mhz analog input dynamic accuracy the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C 1dbfs. (note 4) symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 78.3 76.0 dbfs dbfs 15mhz input (2.25v range, pga = 0) 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 76.8 77.2 78.2 78.2 76.0 dbfs dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 70mhz input (1.5v range, pga = 1) 74.2 74.7 77.7 75.7 dbfs dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 76.4 74.9 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 75.6 74.2 dbfs dbfs sfdr spurious free dynamic range 2 nd or 3 rd harmonic 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 98 98 dbc dbc 15mhz input (2.25v range, pga = 0) 15mhz input (2.25v range, pga = 0 15mhz input (1.5v range, pga = 1) 85 86 98 98 98 dbc dbc dbc 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 70mhz input (1.5v range, pga = 1) 82 83 90 92 92 dbc dbc dbc 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 88 90 dbc dbc 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 80 82 dbc dbc
ltc2205-14 4 220514fa dynamic accuracy the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs unless otherwise noted. (note 4) symbol parameter conditions min typ max units sfdr spurious free dynamic range 4 th harmonic or higher 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 103 103 dbc dbc 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 87 98 98 dbc dbc 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 86.5 98 98 dbc dbc 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 95 95 dbc dbc 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 93 93 dbc dbc s/(n+d) signal-to-noise plus distortion ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 78.2 75.9 dbfs dbfs 15mhz input (2.25v range, pga = 0) 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 76.7 77.1 78.1 78.1 75.9 dbfs dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 70mhz input (1.5v range, pga = 1) 73.5 74.0 77.4 75.5 75.5 dbfs dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 75.9 74.7 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 73.6 73.2 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither off 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 103 103 dbfs dbfs 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 103 103 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 103 103 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 98 98 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 98 98 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither on 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 113 113 dbfs dbfs 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 95 113 113 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 110 110 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 110 110 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 103 103 dbfs dbfs
ltc2205-14 5 220514fa common mode bias characteristics parameter conditions min typ max units v cm output voltage i out = 0 1.15 1.25 1.35 v v cm output tempco i out = 0 40 ppm/c v cm line regulation 3.135v v dd 3.465v 1 mv/ v v cm output resistance 1ma | i out | 1ma 1 the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) power requirements digital inputs and digital outputs the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 7) 0.2 v v icm common mode input voltage internally set 1.6 v externally set (note 7) 1.2 3.0 v r in input resistance (see figure 2) 6 k c in input capacitance (note 7) 3 pf logic inputs (dith, pga, shdn, rand) v ih high level input voltage v dd = 3.3v 2 v v il low level input voltage v dd = 3.3v 0.8 v i in digital input current v in = 0v to v dd 10 a c in digital input capacitance (note 7) 1.5 pf logic outputs ov dd = 3.3v v oh high level output voltage v dd = 3.3v i o = C10a 3.299 v i o = C200a 3.1 3.29 v v ol low level output voltage v dd = 3.3v i o = 160a 0.01 v i o = 1.6ma 0.10 0.4 v i source output source current v out = 0v C50 ma i sink output sink current v out = 3.3v 50 ma ov dd = 2.5v v oh high level output voltage v dd = 3.3v i o = C200a 2.49 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v ov dd = 1.8v v oh high level output voltage v dd = 3.3v i o = C200a 1.79 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v dd analog supply voltage 3.315 3.3 3.465 v p shdn shutdown power shdn = v dd 0.2 mw ov dd output supply voltage 0.5 3.3 3.6 v i vdd analog supply current 181 212 ma p dis power dissipation 597 700 mw
ltc2205-14 6 220514fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd, with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, f sample = 65mhz differential enc + /enc C = 2v p-p sine wave with 1.6v common mode, input range = 2.25v p-p with differential drive (pga = 0), unless otherwise speci? ed. note 5: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C1/2lsb when the output code ? ickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min max units f s sampling frequency 1 65 mhz t l enc low time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) 6.40 4.60 7.69 7.69 500 500 ns ns t h enc high time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) 6.40 4.60 7.69 7.69 500 500 ns ns t ap sample-and-hold aperture delay 0.7 ns t d enc to data delay (note 7) 1.3 2.7 4.0 ns t c enc to clkout delay (note 7) 1.3 2.7 4.0 ns t skew data to clkout skew (t d C t c ) (note 7) C0.6 0 0.6 ns t oe data access time bus relinquish time cl = 5pf (note 7) (note 7) 5 5 15 15 ns ns pipeline latency 7 cycles timing characteristics
ltc2205-14 7 220514fa typical performance characteristics ltc2205-14: inl (integral nonlinearity) vs code ltc2205-14: dnl (differential nonlinearity) vs code ltc2205-14: grounded input histogram ltc2205-14: 32k point fft, C1dbfs, f in = 5.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C1dbfs, f in = 5.1mhz, pga = 1, dith = 0 ltc2205-14: 32k point fft, C25dbfs, f in = 5.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C25dbfs, f in = 5.1mhz, pga = 0, dith = 1 ltc2205-14: 32k point fft, C40dbfs, f in = 5.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C40dbfs, f in = 5.1mhz, pga = 0, dith = 1 code 0 ?1.5 inl (lsb) ?1.0 ?0.5 0 0.5 4096 8192 12288 16384 220514 g01 1.0 1.5 code 0 dnl (lsb) 0 0.50 16384 220514 g02 ?0.50 ?1.00 4096 8192 12288 1.00 ?0.25 0.25 ?0.75 0.75 code 8175 count 150,000 200,000 250,000 8179 220514 g03 100,000 50,000 0 8176 8177 8178 8180 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g04 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g05 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g06 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g07 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g08 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g09 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30
ltc2205-14 8 220514fa ltc2205-14: 32k point fft, C1dbfs, f in = 15.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C1dbfs, f in = 15.1mhz, pga = 1, dith = 0 ltc2205-14: 32k point fft, C25dbfs, f in = 15.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C25dbfs, f in = 15.1mhz, pga = 0, dith = 1 ltc2205-14: 32k point fft, C40dbfs, f in = 15.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C40dbfs, f in = 15.1mhz, pga = 0, dith = 1 ltc2205-14: 32k point fft, C1dbfs, f in = 70.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C25dbfs, f in = 70.1mhz, pga = 1, dith = 0 ltc2205-14: 32k point fft, C25dbfs, f in = 70.1mhz, pga = 0, dith = 1 typical performance characteristics frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g10 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g11 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g12 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g13 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g14 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g15 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g16 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g17 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g19 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30
ltc2205-14 9 220514fa ltc2205-14: 32k point fft, C40dbfs, f in = 70.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C40dbfs, f in = 70.1mhz, pga = 0, dith = 1 ltc2205-14: 32k point fft, C1dbfs, f in = 140.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C1dbfs, f in = 140.1mhz, pga = 1, dith = 0 ltc2205-14: 32k point fft, C25dbfs, f in = 140.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C25dbfs, f in = 140.1mhz, pga = 0, dith = 1 typical performance characteristics frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g20 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g21 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g22 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g23 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g24 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g25 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g26 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g27 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 ltc2205-14: 32k point fft, C40dbfs, f in = 140.1mhz, pga = 0, dith = 0 ltc2205-14: 32k point fft, C40dbfs, f in = 140.1mhz, pga = 0, dith = 1 ltc2205-14: 32k point fft, f in1 = 14.9mhz, C7dbfs, f in2 = 20.1mhz, C7dbfs, pga = 0, dith = 1 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g28 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30
ltc2205-14 10 220514fa ltc2205-14: sfdr vs input level, f in = 5.1mhz, rand = 1, dith = 1 typical performance characteristics ltc2205-14: 32k point fft, f in1 = 64.1mhz, C7dbfs, f in2 = 70.1mhz, C7dbfs, pga = 0, dith = 0 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 220514 g29 ?100 ?110 ?120 ?40 ?60 ?90 ?30 ?130 ?50 ?70 515 30 input level (dbfs) ?80 20 sfdr (dbfs and dbc) 30 50 60 70 120 90 ?60 ?40 ?30 220514 g30 40 100 110 80 ?70 ?50 ?20 ?10 0 input level (dbfs) ?80 20 sfdr (dbfs and dbc) 30 50 60 70 120 90 ?60 ?40 ?30 220514 g31 40 100 110 80 ?70 ?50 ?20 ?10 0 input level (dbfs) ?80 20 sfdr (dbfs and dbc) 30 50 60 70 120 90 ?60 ?40 ?30 220514 g32 40 100 110 80 ?70 ?50 ?20 ?10 0 ltc2205-14: sfdr vs input level, f in = 14.9mhz, rand = 1, dith = 0 ltc2205-14: sfdr vs input level, f in = 14.9mhz, rand = 1, dith = 1 input level (dbfs) ?80 20 sfdr (dbfs and dbc) 30 50 60 70 120 90 ?60 ?40 ?30 220514 g33 40 100 110 80 ?70 ?50 ?20 ?10 0 ltc2205-14: sfdr vs input level, f in = 70.1mhz, rand = 1, dith = 0 ltc2205-14: sfdr vs input level, f in = 70.9mhz, rand = 1, dith = 1 ltc2205-14: sfdr vs input level, f in = 140.1mhz, rand = 1, dith = 0 input level (dbfs) ?80 20 sfdr (dbfs and dbc) 30 50 60 70 120 90 ?60 ?40 ?30 220514 g34 40 100 110 80 ?70 ?50 ?20 ?10 0 input level (dbfs) ?80 20 sfdr (dbfs and dbc) 30 50 60 70 120 90 ?60 ?40 ?30 220514 g35 40 100 110 80 ?70 ?50 ?20 ?10 0 input level (dbfs) ?80 20 sfdr (dbfs and dbc) 30 50 60 70 120 90 ?60 ?40 ?30 220514 g36 40 100 110 80 ?70 ?50 ?20 ?10 0 ltc2205-14: sfdr vs input level, f in = 5.1mhz, rand = 1, dith = 0 ltc2205-14: sfdr vs input level, f in = 140.1mhz, rand = 1, dith = 1 input level (dbfs) ?80 20 sfdr (dbfs and dbc) 30 50 60 70 120 90 ?60 ?40 ?30 220514 g37 40 100 110 80 ?70 ?50 ?20 ?10 0
ltc2205-14 11 220514fa typical performance characteristics ltc2205-14: sfdr vs input frequency, rand = 1, dith = 1 ltc2205-14: snr vs input frequency, rand = 1, dith = 0 ltc2205-14: sfdr and snr vs sample rate, f in = 5.1mhz, rand = 0, dith = 0 sample rate (msps) 0 sfdr (dbc) and snr (dbfs) 90 100 80 220514 g40 80 70 20 40 50 100 110 60 10 30 90 70 sfdr snr ltc2205-14: sfdr and snr vs supply voltage, f in = 5.1mhz, rand = 0, dith = 0 supply voltage (v) 2.4 70 sfdr (dbc) and snr (dbfs) 80 90 100 110 2.6 2.8 3.0 sfdr snr 3.2 220514 g41 3.4 3.6 ltc2205-14: i vdd vs sample rate, f in = 5.1mhz, rand = 0, dith = 0 ltc2205-14: gain drift with internal reference vs temperature sample rate (msps) i vdd (ma) 180 200 220 80 220214 g42 160 140 170 190 210 150 130 20 40 60 10 090 30 50 70 100 100 v dd = 3.47v v dd = 3.13v v dd = 3.3v temperature ( c) ?60 gain drift (% fs) ?0.15 ?0.05 100 220514 g43 ?0.25 ?0.35 ?20 20 60 ?40 0 40 80 0.05 ?0.20 ?0.10 ?0.30 0 input frequency (mhz) 0 sfdr (dbc) 90 100 200 220414 g38 80 70 50 100 150 250 110 pga = 1 pga = 0 input frequency (mhz) 0 73 snr (dbfs) 74 75 76 77 78 79 50 100 pga = 0 pga = 1 150 200 220514 g39 250
ltc2205-14 12 220514fa sense (pin 1): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.25v (pga = 0). v cm (pin 2): 1.25v output. optimum voltage for input com- mon mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recommended. v dd (pins 3, 4, 12, 13, 14): 3.3v analog supply pin. bypass to gnd with 0.1f ceramic chip capacitors. gnd (pins 5, 8, 11, 15, 48): adc power ground. a in + (pin 6): positive differential analog input. a in C (pin 7): negative differential analog input. enc + (pin 9): positive differential encode input. the sampled analog input is held on the rising edge of enc + . internally biased to 1.6v through a 6.2k resistor. output data can be latched on the rising edge of enc + . enc C (pin 10): negative differential encode input. the sampled analog input is held on the falling edge of enc C . internally biased to 1.6v through a 6.2k resistor. by- pass to ground with a 0.1f capacitor for a single-ended encode signal. shdn (pin 16): power shutdown pin. shdn = low results in normal operation. shdn = high results in powered down analog circuitry and the digital outputs placed in a high impedance state. dith (pin 17): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of this data sheet for details on dither operation. nc (pins 18, 19): no connect. d0-d13 (pins 20-22, 26-28, 32-35 and 39-42): digital outputs. d13 is the msb. ognd (pins 23, 31 and 38): output driver ground. ov dd (pins 24, 25, 36, 37): positive supply for the out- put drivers. bypass to ground with 0.1f ceramic chip capacitors. clkout C (pin 29): data valid output. clkout C will toggle at the sample rate. latch the data on the falling edge of clkout C . clkout + (pin 30): inverted data valid output. clkout + will toggle at the sample rate. latch the data on the rising edge of clkout + . of (pin 43): over/under flow digital output. of is high when an over or under ? ow has occurred. ? o ? e (pin 44): output enable pin. low enables the digital output drivers. high puts digital outputs in hi-z state. mode (pin 45): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects offset binary output format and enables the clock duty cycle sta- bilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin 46): digital output randomization selection pin. rand low results in normal operation. rand high selects d1-d13 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. this mode of operation reduces the effects of digital output interferance. pga (pin 47): programmable gain ampli? er control pin. low selects a front-end gain of 1, input range of 2.25v p-p . high selects a front-end gain of 1.5, input range of 1.5v p-p . gnd (exposed pad, pin 49): adc power ground. the exposed pad on the bottom of the package must be sol- dered to ground. pin functions
ltc2205-14 13 220514fa figure 1. functional block diagram block diagram adc clocks differential input low jitter clock driver dither signal generator first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage enc + enc ? correction logic and shift register dith m0de ognd clkout+ clkout ? of d13 d12 ov dd d1 d0 220514 f01 input s/h a in ? a in + third pipelined adc stage output drivers control logic pga rand oe shdn v dd gnd pga sense v cm buffer adc reference voltage reference range select timing diagram t h t d t c t l n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 analog input enc ? enc + clkout ? clkout + d0-d13, of 220514 td01 t ap n + 1 n + 2 n + 4 n + 3 n
ltc2205-14 14 220514fa dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band lim- ited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the ? rst ? ve harmonics. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log v v v v v n =+++ () ? ... / 20 2 2 3 2 4 22 1 2 where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 3rd order imd terms include (2fa + fb), (fa + 2fb), (2fa C fb) and (fa C 2fb). the 3rd order imd is de? ned as the ratio of the rms value of either input tone to the rms value of the largest 3rd order imd product. spurious free dynamic range (sfdr) the ratio of the rms input signal amplitude to the rms value of the peak spurious spectral component expressed in dbc. sfdr may also be calculated relative to full scale and expressed in dbfs. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when a rising enc + equals the enc C voltage to the instant that the input signal is held by the sample- and-hold circuit. aperture delay jitter the variation in the aperture delay time from convertion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) operation
ltc2205-14 15 220514fa converter operation the ltc2205-14 is a cmos pipelined multi-step converter with a front-end pga. as shown in figure 1, the converter has ? ve pipelined adc stages; a sampled analog input will result in a digitized value seven cycles later (see the timing diagram section). the analog input is differential for improved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. the encode input is also differential for improved common mode noise immunity. the ltc2205-14 has two phases of operation, determined by the state of the differential enc + /enc C input pins. for brevity, the text will refer to enc + greater than enc C as enc high and enc + less than enc C as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and a residue ampli? er. in opera- tion, the adc quantizes the input to the stage, and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages operate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when enc is low, the analog input is sampled differen- tially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the voltage on the sample capacitors is held. while enc is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h ampli? er during the high phase of enc. when enc goes back low, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the ? fth stage for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2205-14 cmos differential sample and hold. the differential ana- log inputs are sampled directly onto sampling capacitors (c sample ) through nmos transitors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc is low, the nmos transistors connect the analog inputs to the sampling capacitors which charge to, and track the differential in- put voltage. when enc transitions from low to high, the sampled input voltage is held on the sampling capacitors. figure 2. equivalent input circuit applications information c sample 4.9pf v dd v dd ltc2005-14 r parasitic 3 ? r on 20 ? r on 20 ? r parasitic 3 ? a in + 220514 f02 c sample 4.9pf v dd a in ? enc ? enc + 1.6v 6k 1.6v 6k c parasitic 1.8pf c parasitic 1.8pf
ltc2205-14 16 220514fa during the hold phase when enc is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve speci? ed performance. each input should swing 0.5625v for the 2.25v range (pga = 0) or 0.375v for the 1.5v range (pga = 1), around a common mode voltage of 1.25v. the v cm output pin (pin 2) is designed to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with 2.2f or greater. input drive impedence as with all high performance, high speed adcs the dy- namic performance of the ltc2205-14 can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can in? uence sfdr. at the falling edge of enc the sample-and-hold circuit will connect the 4.9pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when enc rises, holding the sampled input on the sampling capacitor. ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance it is recomended to have a source impedence of 100 or less for each input. the source impedence should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits input filtering a ? rst order rc lowpass ? lter at the input of the adc can serve two functions: limit the noise from input circuitry and provide isolation from adc s/h switching. the ltc2205-14 has a very broadband s/h circuit, dc to 700mhz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recommended rc ? lter. figures 3, 4a and 4b show three examples of input rc ? ltering at three ranges of input frequencies. in general it is desirable to make the capacitors as large as can be toleratedthis will help suppress random noise as well as noise coupled from the digital circuitry. the ltc2205-14 does not require any input ? lter to achieve data sheet speci? cations; however, no ? ltering will put more stringent noise requirements on the input drive circuitry. transformer coupled circuits figure 3 shows the ltc2205-14 being driven by an rf transformer with a center-tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the adc. source impedance greater than 50 can reduce the input bandwidth and increase high frequency distor- tion. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. applications information
ltc2205-14 17 220514fa figure 3. single-ended to differential conversion using a transformer. recommended for input frequencies from 5mhz to 150mhz figure 4a. using a transmission line balun transformer. recommended for input frequencies from 150mhz to 250mhz figure 4b. using a transmission line balun transformer. recommended for input frequencies from 250mhz to 500mhz direct coupled circuits figure 5 demonstrates the use of a differential ampli? er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop ampli? er will de- grade the adc sfdr at high input frequencies. additionally, wideband op amps or differential ampli? ers tend to have high noise. as a result, the snr will be degraded unless the noise bandwidth is limited prior to the adc input. center-tapped transformers provide a convenient means of dc biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. figure 4a shows transformer coupling using a transmis- sion line balun transformer. this type of transformer has much better high frequency response and balance than ? ux coupled center tap transformers. coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25v. figure 4b shows the same circuit with components suitable for higher input frequencies. applications information 35 ? 5 ? 35 ? 10 ? 10 ? 5 ? 5 ? 0.1 f a in + a in ? 8.2pf 2.2 f 8.2pf 8.2pf v cm t1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size except 2.2 f 220514 f03 ltc2205-14 0.1 f a in + a in ? 4.7pf 2.2 f 4.7pf 4.7pf v cm ltc2205-14 analog input 0.1mf 0.1mf t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2mf 220514 f04a 5 ? 10 ? 25 ? 25 ? 10 ? 5 ? 0.1 f a in + a in ? 2.2 f 2.2pf 2.2pf v cm ltc2205-14 analog input 0.1 f 0.1 f t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2 f 22054 f04b 5 ? 25 ? 25 ? 5 ?
ltc2205-14 18 220514fa figure 7. a 2.25v range adc with an external 2.5v reference reference operation figure 6 shows the ltc2205-14 reference circuitry con- sisting of a 2.5v bandgap reference, a programmable gain ampli? er and control circuit. the ltc2205-14 has three modes of reference operation: internal reference, 1.25v external reference or 2.5v external reference. to use the internal reference, tie the sense pin to v dd . to use an external reference, simply apply either a 1.25v or 2.5v reference voltage to the sense input pin. both 1.25v and 2.5v applied to sense will result in a full-scale range of 2.25v p-p (pga = 0). a 1.25v output, v cm is provided for a common mode bias for input drive circuitry. an external bypass capacitor is required for the v cm output. this provides a high frequency low impedance path to ground for internal and external circuitry. this is also the compensation capacitor for the reference; it will not be stable without this capacitor. the minimum value required for stability is 2.2f. the internal programmable gain ampli? er provides the internal reference voltage for the adc. this ampli? er has very stringent settling requirements and is not accessible for external use. applications information pga 1.25v sense v cm buffer internal adc reference range select and gain control 2.5v bandgap reference 2.2 f tie to v dd to use internal 2.5v reference or input for external 2.5v reference or input for external 1.25v reference 220514 f06 ltc2205-14 figure 6. reference circuit v cm sense 1.25v 3.3v 2.2 f 2.2 f 1 f 220514 f07 ltc2205-14 ltc1461-2.5 2 6 4 figure 5. dc coupled input with differential ampli? er ? ? + + a in + a in ? 2.2 f 12pf 12pf v cm ltc2205-14 analog input 220514 f05 cm amplifier = ltc6600-20, ltc1993, etc. high speed differential amplifier 25 ? 25 ? the sense pin can be driven 5% around the nominal 2.5v or 1.25v external reference inputs. this adjustment range can be used to trim the adc gain error or other system gain errors. when selecting the internal reference, the sense pin should be tied to v dd as close to the converter as possible. if the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1f (or larger) ceramic capacitor.
ltc2205-14 19 220514fa figure 8. transformer driven encode any noise present on the encode signal will result in ad- ditional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies), take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude possible. if using trans- former coupling, use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a ? xed frequency sinusoidal signal, ? lter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.2v to 3v. each input may be driven from ground to v dd for single-ended drive. applications information v dd v dd ltc2205-14 220514 f08 v dd 1.6v 1.6v 6k 6k to internal adc clock drivers enc ? enc + etc1-1t 0.1 f 33pf encode input 100 ? 50 ? 0.1 f 50 ? pga pin the pga pin selects between two gain settings for the adc front-end. pga = 0 selects an input range of 2.25v p-p ; pga = 1 selects an input range of 1.5v p-p . the 2.25v input range has the best snr; however, the distortion will be higher for input frequencies above 100mhz. for applica- tions with high input frequencies, the low input range will have improved distortion; however, the snr will be worse by up to approximately 2db. see the typical performance characteristics section. driving the encode inputs the noise performance of the ltc2205-14 can depend on the encode signal quality as much as on the analog input. the encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 1.6v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits.
ltc2205-14 20 220514fa the lower limit of the ltc2205-14 sample rate is determined by droop of the sample and hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the speci? ed minimum operating frequency for the ltc2205-14 is 1msps. digital outputs digital output buffers figure 11 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output eliminates the need for external damping resistors. as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the ltc2205-14 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as a alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the output may be used but is not required since the adc has a series resistor of 33 on chip. lower ov dd voltages will also help reduce interference from the digital outputs. maximum and minimum encode rates the maximum encode rate for the ltc2205-14 is 65msps. for the adc to operate properly the encode signal should have a 50% (2.5%) duty cycle. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. when using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. an optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. this circuit uses the rising edge of enc pin to sample the analog input. the falling edge of enc is ignored and an internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin must be connected to 1/3v dd or 2/3v dd using external resistors. applications information ltc2205-14 220514 f11 ov dd v dd v dd 0.1 f typical data output ognd ov dd 0.5v to 3.6v predriver logic data from latch 33 ? figure 11. equivalent circuit for a digital output buffer figure 10. enc drive using a cmos to pecl translator figure 9. single-ended enc drive, not recommended for low jitter 220514 f09 enc ? 1.6v v threshold = 1.6v enc + 0.1 f ltc2205-14 220514 f10 enc ? enc + 3.3v 3.3v d0 q0 q0 130 ? 130 ? 83 ? 83 ? mc100lvelt22 ltc2205-14
ltc2205-14 21 220514fa figure 12. functional equivalent of digital output randomizer data format the ltc2205-14 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the mode pin. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistor divider can be user to set the 1/3v dd and 2/3v dd logic levels. table 1 shows the logic states for the mode pin. table 1. mode pin function mode output format clock duty cycle stabilizer 0(gnd) offset binary off 1/3v dd offset binary on 2/3v dd 2s complement on v dd 2s complement off over? ow bit an over? ow output bit (of) indicates when the converter is over-ranged or under-ranged. a logic high on the of pin indicates an over? ow or under? ow. output clock the adc has a delayed version of the encode input available as a digital output. both a noninverted version, clkout+ and an inverted version clkoutC are provided. the clkout+/clkoutC can be used to synchronize the con- verter data to the digital system. this is necessary when using a sinusoidal encode. data can be latched on the rising edge of clkout+ or the falling edge of clkoutC. clkout+ falls and clkoutC rises as the data outputs are updated. digital output randomizer interference from the adc digital outputs is sometimes unavoidable. interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can result in discernible unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise ? oor for a large reduction in unwanted tone amplitude. applications information clkout of d13/d0 d12/d0 d2/d0 d1/d0 d0 d0 d1 rand = high, scramble enabled d2 d12 d13 of ltc2205-14 clkout rand 220514 f12 the digital output is randomized by applying an exclu- sive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied; that is, an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout output are not affected. the output randomizer function is active when the rand pin is high. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. ov dd can be powered with any logic voltage up to the v dd of the adc. ognd can be powered with any voltage from ground up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd .
ltc2205-14 22 220514fa internal dither the ltc2205-14 is a 14-bit adc with a very linear transfer function; however, at low input levels even slight imperfec- tions in the transfer function will result in unwanted tones. small errors in the transfer function are usually a result of adc element mismatches. an optional internal dither mode can be enabled to randomize the input location on the adc transfer curve, resulting in improved sfdr for low signal levels. as shown in figure 14, the output of the sample-and-hold ampli? er is summed with the output of a dither dac. the dither dac is driven by a long sequence pseudo-random number generator; the random number fed to the dither dac is also subtracted from the adc result. if the dither dac is precisely calibrated to the adc, very little of the dither signal will be seen at the output. the dither signal that does leak through will appear as white noise. the dither dac is calibrated to result in less than 0.5db elevation in the noise ? oor of the adc, as compared to the noise ? oor with dither off. applications information figure 13. descrambling a scrambled digital output figure 14. functional equivalent block diagram of internal dither circuit +? ain ? ain + s/h amp digital summation output drivers multibit deep pseudo-random number generator 14-bit pipelined adc core precision dac clock/duty cycle control clkout of d13 d0 enc dither enable high = dither on low = dither off dith enc analog input 220514 f14 ltc2205-14 d1 d0 d2 d12 d13 ltc2205-14 pc board fpga clkout of d13/d0 d12/d0 d2/d0 d1/d0 d0 22054 f13
ltc2205-14 23 220514fa applications information grounding and bypassing the ltc2205-14 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltc2205-14 has been optimized for a ? owthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd, v cm , and ov dd pins. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc2205-14 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2205-14 is trans- ferred from the die through the bottom-side exposed pad. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. it is critical that the exposed pad and all ground pins are connected to a ground plane of suf? cient area with as many vias as possible.
ltc2205-14 24 220514fa applications information ordering guide: demo board number part number resolution speed input frequency usb i/f board dc918a-a ltc2207cuk 16-bit 105msps 1mhz to 70mhz dc718 dc918a-b ltc2207cuk 16-bit 105msps 70mhz to 140mhz dc718 dc918a-c ltc2206cuk 16-bit 80msps 1mhz to 70mhz dc718 dc918a-d ltc2206cuk 16-bit 80msps 70mhz to 140mhz dc718 dc918a-e ltc2205cuk 16-bit 65msps 1mhz to 70mhz dc718 dc918a-f ltc2205cuk 16-bit 65msps 70mhz to 140mhz dc718 dc918a-g ltc2204cuk 16-bit 40msps 1mhz to 70mhz dc718 dc918a-h ltc2207cuk-14 14-bit 105msps 1mhz to 70mhz dc718 dc918a-i ltc2207cuk-14 14-bit 105msps 70mhz to 140mhz dc718 dc918a-j ltc2206cuk-14 14-bit 80msps 1mhz to 70mhz dc718 dc918a-k ltc2206cuk-14 14-bit 80msps 70mhz to 140mhz dc718 dc918a-l ltc2205cuk-14 14-bit 65msps 1mhz to 70mhz dc718 see web site for ordering details or contact local sales.
ltc2205-14 25 220514fa silkscreen top applications information top side inner layer 2 inner layer 3
ltc2205-14 26 220514fa applications information inner layer 4 inner layer 5 bottom side silkscreen bottom
ltc2205-14 27 220514fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704) package description 7.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 chamfer c = 0.35 0.40 0.10 48 47 1 2 bottom view?exposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ
ltc2205-14 28 220514fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0506 rev a ? printed in usa related parts part number description comments ltc1748 14-bit, 80msps 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr lt1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain lt1994 low noise, low distortion fully differential input/ output ampli? er/driver low distortion: C94dbc at 1mhz ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 140mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2203 16-bit, 25msps, 3.3v adc, lowest noise 220mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2204 16-bit, 40msps, 3.3v adc 480mw, 79.1db snr, 100db sfdr, 48-pin qfn ltc2205 16-bit, 65msps, 3.3v adc 610mw, 79db snr, 100db sfdr, 48-pin qfn ltc2206 16-bit, 80msps, 3.3v adc 725mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2207 16-bit, 105msps, 3.3v adc 900mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3,3v adc, lvds outputs 1250mw, 77.9db snr, 100db sfdr, 64-pin qfn ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain 450mhz to 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator lt5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz. nf = 12.5db, 50w single ended rf and lo ports

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